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ADT7467
Table 63. REGISTER 0X63 ? ENHANCED ACOUSTICS REGISTER 2 (POWER-ON DEFAULT = 0X00)
Bit
<2:0>
<3>
<6:4>
<7>
Name
ACOU3
EN3
ACOU2
EN2
R/W (Note 1)
Read/Write
Read/Write
Read/Write
Read/Write
Description
These bits select the ramp rate applied to the PWM3 output. Instead of PWM3 jumping instant-
aneously to its newly calculated speed, PWM3 ramps gracefully at the rate determined by
these bits. This effect enhances the acoustics of the fan being driven by the PWM3 output.
Time Slot Increase
Time for 33% to 100%
000 = 1
35 sec
001 = 2
17.6 sec
010 = 3
11.8 sec
011 = 5
7 sec
100 = 8
4.4 sec
101 = 12
3 sec
110 = 24
1.6 sec
111 = 48
0.8 sec
When this bit is 1, acoustic enhancement is enabled on PWM3 output.
These bits select the ramp rate applied to the PWM2 output. Instead of PWM2 jumping instant-
aneously to its newly calculated speed, PWM2 ramps gracefully at the rate determined by
these bits. This effect enhances the acoustics of the fans being driven by the PWM2 output.
Time Slot Increase
Time for 33% to 100%
000 = 1
35 sec
001 = 2
17.6 sec
010 = 3
11.8 sec
011 = 5
7 sec
100 = 8
4.4 sec
101 = 12
3 sec
110 = 24
1.6 sec
111 = 48
0.8 sec
When this bit is 1, acoustic enhancement is enabled on PWM2 output.
1. This register becomes a read-only register when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to this
register fail.
Table 64. PWM MINIMUM DUTY CYCLE REGISTERS
Register Address
0x64
0x65
0x66
R/W (Note 1)
Read/Write
Read/Write
Read/Write
Description
PWM1 Minimum Duty Cycle
PWM2 Minimum Duty Cycle
PWM3 Minimum Duty Cycle
Power-On Default
0x80 (50% Duty Cycle)
0x80 (50% Duty Cycle)
0x80 (50% Duty Cycle)
1. These registers become read-only registers when the ADT7467 is in automatic fan control mode.
Table 65. REGISTER 0x64, REGISTER 0x65, AND REGISTER 0x66 ? PWM1, PWM2, and PWM3
Minimum Duty Cycle Registers
Bit
<7:0>
R/W (Note 1)
Read/Write
Description
These bits define the PWM MIN duty cycle for PWMx.
0x00 = 0% Duty Cycle (Fan Off)
0x40 = 25% Duty Cycle
0x80 = 50% Duty Cycle
0xFF = 100% Duty Cycle (Fan Full Speed)
1. These registers become read-only registers when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to
these registers fail.
Table 66. T MIN REGISTERS (Note 1)
Register Address
0x67
0x68
0x69
R/W (Note 2)
Read/Write
Read/Write
Read/Write
Description
Remote 1 T MIN
Local T MIN
Remote 2 T MIN
Power-On Default
0x9A (90 ? C)
0x9A (90 ? C)
0x9A (90 ? C)
1. These are the T MIN registers for each temperature channel. When the temperature measured exceeds T MIN , the appropriate fan runs at
minimum speed and increases with temperature according to T RANGE .
2. These registers become read-only registers when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to
these registers fail.
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